Preliminary Specifications: Programmed Data Processor Model Three (PDP-3) October, 1960 — Background and Themes

Design Philosophy in the Introduction

The introduction frames the PDP-3 as a machine built on restraint. The phrase "system design restraint" is not merely descriptive but prescriptive, suggesting a deliberate avoidance of complexity. The text states that this restraint "excludes many marginal or superfluous features and thus their attendant cost and maintenance problems." This language positions the PDP-3 as a practical tool for "complex real time control applications" and "the center of a modern computing facility." The emphasis on economy and reliability over raw power is evident in the average instruction rate of 100,000 operations per second, with a peak of 200,000. The document does not boast of theoretical maxima but presents a balanced performance profile.

Instruction Format and Addressing Details

The central processor section describes a single-address, single-instruction machine operating on 36-bit numbers. It features "multiple step indirect addressing and indexing of addresses," with 511 registers available as index registers. The instruction format is not fully excerpted, but the mention of "left 6 bits" communicating with the Instruction Register hints at a fixed-width opcode. The memory is organized in 4096-word core modules, with a cycle time of five microseconds. The system can address 8 modules natively and expand to 64. This modular memory design aligns with the overall philosophy of scalability without overcomplication.

Input-Output Modes and Asynchronous Operation

The input-output section reveals careful attention to real-time interaction. The paper tape reader operates in alphanumeric and binary modes, with the binary mode using the eighth hole for synchronization. The typewriter input is described as "completely asynchronous," handled by setting a program flag when a key is struck. The text notes that the code "will remain at the gate for a relatively long time by virtue of the slow mechanical action," a rare moment where the document acknowledges physical constraints. The optional Sequence Break System introduces 16 interrupt channels in a priority chain, enabling concurrent device operation. This system stores register contents in fixed memory locations, showing early interrupt handling design.

Readers approaching this specification should note its dual audience: engineers evaluating the machine and programmers needing exact operational details. The document's clarity and avoidance of marketing language make it a reliable primary source for understanding 1960s computer design. Pay attention to the interplay between hardware descriptions and the implied programming model, especially in the input-output sections where asynchronous behavior is explicitly addressed.

Reading this PDP-3 specification, I remembered my father’s old workshop manuals—pages of exact diagrams that felt like quiet promises. The precision here, the careful modularity, reminds me of leafing through Outspinning the Spider: The Story of Wire and Wire Rope — Inside the Classic years ago, where the tensile strength of simple strands became something almost human. Both books hum with the same patient faith in structure holding firm.